Modeling, Analysis and Optimization of Interconnects in Deep Submicron Regime

Abstract

Integrated circuit technology is the base for all modern electronic systems. The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. This has led to the tremendous growth in integrated circuits technology resulting in highly complex circuits with increasing number of components and on-chip interconnects. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-a-vis the logic in determining the overall performance. Alt ` hough active devices mostly benefited from scaling, intermediate and global interconnects performance has degraded with scaling. Prominent reason being long interconnects do not scale with the technology. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. This thesis addresses the issues associated with the on-chip long interconnects, namely, modeling, delay reduction , minimization of signal reflection at high frequencies at the interconnect-via junction and reducing the skew in clock signals. Design and analysis methodologies presented in this work focus on improving the performance of the interconnects in DSM regime. Interconnects are represented by distributed RLGC networks and modeled using state space approach. Generalized state space matrices are derived for Single, Coupled, iiiL and T type of interconnects and these models are used to estimate interconnect metrics. Using the coupled interconnect models, crosstalk noise in the victim lines of the multi-coupled interconnects is estimated. Further, model order reduction using moment matching is employed to reduce the large order of the RLGC network to lower order for reducing the complexity of the network. As an alternative to traditional repeater insertion method to reduce the intermediate/global interconnect delay, exploiting the resonant characteristics of the interconnects is gaining popularity. The idea of this method is to make a resonating interconnect by inserting an inductor of appropriate value along the interconnect to nullify the effect of interconnect parasitic capacitance. This scheme can be effectively used for clock signals as well as signal modulated data networks. At high frequencies, impedance discontinuities at interconnect-via junction results in signal reflections and give rise to signal integrity problems. A methodology to minimize the via-induced signal reflections by the inclusion of an appropriate capacitive load is presented. Clocks being the highest frequency signals in any IC, delay and skew of a few pico seconds in the transmitted clock signals is detrimental for the proper functioning of the circuit. Traditionally, metamaterial structures are used to introduce desired phase shifts in microwave circuit applications. The Composite Right/Left Handed (CRLH) metamaterial structure has a unique feature of supporting an infinite wavelength at a nonzero frequency. This property of CRLH is leveraged to reduce the skew in the transmission of high speed clock signals over long