Please use this identifier to cite or link to this item: https://idr.l4.nitk.ac.in/jspui/handle/123456789/7110
Title: A Resolution Independent 2-Bits-per-Cycle SAR ADC
Authors: Morakhia, A.
Gunnam, S.
Prakash, P.
Kudli, S.
Laxminidhi, T.
Issue Date: 2015
Citation: Proceedings - 2014 5th International Symposium on Electronic System Design, ISED 2014, 2015, Vol., , pp.145-149
Abstract: This paper proposes a resolution independent architecture for SAR ADCs. The proposed architecture uses 2 bits per cycle conversion and is made independent of number of ADC bits. A 2-bit flash ADC is used to compute 2-bits in each iteration. The reference voltage across the resistor divider of the 2-bit flash ADC is changed in each iteration based on the 2-bits resolved in the previous iteration. The reference voltages for each iteration are generated using a pair of modified switched capacitor-based DACs. The new DAC architecture used in the proposed ADC can use the thermometric code output of the 2-bit flash ADC directly, avoiding the need for complex control circuitry. The dependency of DAC architecture on the ADC resolution, observed in conventional SAR ADCs, has been absorbed into the digital logic which is easy to design. The proposed architecture is validated using an 8 bit ADC designed in 0.25 ?m CMOS process. � 2014 IEEE.
URI: http://idr.nitk.ac.in/jspui/handle/123456789/7110
Appears in Collections:2. Conference Papers

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