Area Efficient Hardware Architectures of Intra Prediction and Sample Adaptive Offset Filter for Hevc Encoder

Abstract

High efficiency video coding (HEVC) was developed to handle the ever- increasing amount of video content by providing significant compression gains. HEVC/H.265, developed by JCT-VC, can compress 4 K and 8 K videos with 50% more efficiency than its predecessor H.264. This bit-rate saving lowers infrastructure costs, making high-resolution and high-quality video transmissions more affordable. HEVC can handle HD content and deliver better compression efficiency because of computationally complex algorithms like complex partitions, more angular predictions in intra pre- diction, more parallel tools, a new addition to in-loop filters, and other improved coding tools. The addition of variable sized prediction units (PUs) and 35 directional predictions has improved the compression efficiency while significantly in- creasing the complexity of the intra prediction in HEVC. An efficient hard- ware architecture for the intra prediction is proposed in this thesis which produces high throughput to support high definition (HD) video applica- tions. Features such as a compact reusable reference buffer, a dedicated arithmetic unit are included that reduce hardware resources. The entire ar- chitecture works as a pipelined unit and generates eight samples per clock cycle in parallel with no data dependency. All of the above improvements could not be fully utilised when the intra prediction engine is combined with its subsequent transform module in the HEVC encoder. As a result, an improved parallel-pipelined intra prediction engine is designed, which will always process and predict samples row-by-row so that they can be directly transform coded. The read-write latency associated with fetching reference samples is reduced by incorporating a better compact reconfig- urable reference buffer in the architecture. The in-loop filter of the HEVC encoder and decoder is made up of the deblocking filter (DF) and the newly incorporated sample adaptive offset (SAO) filter, which improves the subjective quality of the image. In this thesis, an integrated in-loop filter is designed on hardware that can handle high computations by using very less on-chip memory. The in-loop filter produces high throughput, while handling external memory traffic and vdependencies to support Ultra HD video applications. The architectures are designed in Verilog HDL (Hardware Description Lan- guage), synthesised, and then implemented on a 28 nm Artix-7 FPGA board with a dual-core ARM Cortex-M1 processor. Xilinx Vivado is used to generate post-implementation reports for analysis. The experimental results show that the proposed designs achieve high throughput while us- ing very little silicon area and have very high hardware efficiency when compared to several other state-of-the-art hardware architectures.