Design and Analysis of Reconfigurable Rf Front End Amplifiers for Wireless Broadband Multimedia Communication

Abstract

This research work focuses on the design and implementation of Microwave Low Noise Amplifiers (LNAs) with built-in techniques for wireless broad- band multimedia communications. The RF front-end blocks account for the majority of the system’s Noise Figure (NF). As a result, low noise designs are being researched to improve the device’s signal-to-noise ratio (SNR). Enhancing the SNR and linearity of the front-end amplifiers sig- nificantly boosts receiver performance. The proposed LNAs’ primary ob- jective is to produce low NF, high flat gain, and excellent linearity while minimizing power consumption at the microwave and millimeter (mm) wave bands of operation. Firstly, a Suspended Substrate Line (SSL) integrated CMOS LNA is pro- posed for low-power 5G wireless receiver systems which are operated in the range of 28GHz to 32GHz. It comprises two stages cascode topology for high gain, better reverse isolation, and improved stability at mm-wave frequencies. A novel SSL-based parallel series network is incorporated between the two cascode stages to provide the required network match- ing and help in enhancing the bandwidth. Prior to incorporation into the design, the proposed SSL is designed and characterized for optimum EM compatibility. The proposed CMOS LNA, which incorporates these novel approaches, will overcome the device’s parasitic and electromagnetic (EM) losses. EM losses in bulk active and passive components have been incurred utilizing built-in approaches to improve LNA linearity. The pro- posed mm-wave LNA enables each component in its family to prevent EM wave leakage and its associated parasitic losses in the layout. The simu- lation and measurement results demonstrate the minimum NF of 2.5dB, the maximum gain of 25dB, and high linearity and stability in the desired band of operation. Secondly, A novel Quasi circulator (QC) integrated LNA operating in 8GHz to 12GHz (X band) is implemented using a two-stage inductive de- generation common source (CS) topology with current reused techniques and variable impedance load. QC provides the minimum insertion loss of 0.9dB with good return and isolation losses. Incorporating QC and opti- v mizing the LNA, the highest flat gain of 30dB with only 0.5dB variation across the entire 4GHz bandwidth and minimum NF of 1dB are achieved simultaneously. The proposed QC-LNA is highly linear, and third-order harmonics are suppressed considerably. It consumes low power and is highly compact. Thirdly, an integrated LNA with a Folded Butterfly Stub Stepped Impedance Resonator (FBSSIR) is also developed by employing packaging technology for a satellite navigation receiver system in the range of 1.6GHz to 2.5GHz. The proposed FBSSIR achieves a more compact structure, controllable transmission zero, adjustable center frequency, and adjustable bandwidth by applying a new structural deformation of a stepped-impedance-resonator (SIR). The core LNA circuit incorporates the proposed FBSSIR as it acts as a filter and the input-output matching network. The proposed FBSSIR- LNA achieves good gain, decent NF, and good linearity by consuming decent power. Finally, a switch-free dual-band reconfigurable LNA in the range of 18GHz to 40GHz (K/Ka-band) is also designed for ultra-wideband wireless ap- plications. It is realized by incorporating inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL). The cascaded CS topology with source degeneration is used in the respective amplifier stages. The proposed inter-stage SSCL splits the amplified input signal from the broad- band driving stage into two parallel single band stages. The corresponding High-band (Ka) and Low-band (K) stages amplify two split-band signals. At the output, the proposed SSCL output stage combines the amplified two single bands. Also, the proposed SSCL provides the necessary net- work matching to the LNA. A single band of operation can be obtained by simply shutting off the drain voltage of the unused transistor band. The proposed LNA achieves an incredibly flat gain of 27dB, ultra-low NF of 1.2dB, and best linear performance with good third-order harmonics suppression at the same time. All the proposed CMOS LNAs are fabricated using a commercial 65nm CMOS process operating with 1.2V supply. DoE and statistical analysis are additional novel contributions towards this thesis work for analyzing vi the proposed LNA designs. Design of Experiment (DoE) is a new analysis technique to find the individual device parameter’s contribution to the final gain, NF, and return loss. Statistical analysis is also performed to find the yield so that the robustness of the proposed designs is satisfied.