Low Power Nonbinary Weighted Successive Approximation Register Analog to Digital Converters

Abstract

Modern instrumentation systems and data acquisition (DAQ) systems demand low to medium resolution, medium speed analog to digital converters (ADC). For DAQ systems with dedicated ADCs per channel, ADC core area is of prime concern to minimize cost/chip. For DAQ systems with a single ADC for multiple channels, it may be required to operate the ADC at different resolutions depending on the channel it is digitizing. In such a case, programmable resolution ADC is an added advantage. Even though the traditional successive approximation register (SAR) ADCs are popular in these applications, they consume large chip area. To optimize ADC over area, nonbinary weighted capacitive (NBWC) digital to analog converter (DAC) architectures are proposed in this work, which makes use of a fixed number of nonbinary weighted capacitors, low power transconductors and switches. Initially, as a proof of concept, a DAC architecture using minimum number of unit size capacitors and buffers is designed for the SAR ADC. In order to enhance sampling speed, a 2 bit per cycle algorithm is developed instead of the conventional 1 bit per cycle evaluation. The designed 8 bit ADC is simulated in 180 nm technology and supply voltage of 3.3V. The ADC designed could achieve a conversion speed of 500 kS/s with a power dissipation of 1.8mW. Integral non linearity (INL) error and differential non linearity (DNL) error are less than 0.5 LSB. The simulated signal to noise and distortion ratio (SNDR) at the input frequency of 56.64 kHz is 48.14 dB and at 232.42 kHz is 47.03 dB. Though the proof of concept ADC simulation results were encouraging, the voltage dependent nature of the parasitic capacitance posed by the switches were found to be the bottleneck in achieving a low value of area efficiency (AE). Therefore, the switched capacitor DAC architecture used in the proof of concept ADC is modified so that the reference generation circuit for the 2 bit per cycle evaluation is least sensitive to parasitics as well as the ADC resolution is made programmable. A programmable 4 to 8 bit DAC is further designed for the SAR ADC with increased sampling rate of 1.2MS/s at 8 bit mode. Passive charge sharing and charge recycling through low power buffers is adopted in the NBWC DAC. A mathematical analysis has also been carried out to justify the parasitic insensitive nature of the reference generation scheme. The proposed idea has been validated by designing a 4 to 8 bit ADC in 90 nm CMOS technology for operations on 1V supply. The post layout simulation of the designed ADC has 1.2MS/s sampling rate at 8 bit mode with a power consumption of 185 μW achieving an effective number of bits (ENOB) of 7.6. The active area of the designed ADC is 0.06mm2, resulting in an AE as low as 295.66 μm2/code. The DAC resolution scaling and the use of variable sampling rate maximizes efficiency at lower resolutions. Therefore figure-of-merit (FOM) degrades only by a factor 4.7 for resolution scaling from 8 bits to 4 bits. This is a significant improvement over the 16x degradation expected from 8 bit to 4 bit resolution scaling by truncating the bits. Another work, as part of this thesis, is exploring switched capacitor integrator (SCI), NBW-CDAC based SAR ADC. The objective is to develop resolution independent, programmable resolution architecture using minimum number of NBW capacitors and switches for fully differential approach. A compact SC integrator based nonbinary weighted 10 bit SAR ADC is designed for low power portable devices and data acquisition systems. This technique requires an operational transconductance amplifier (OTA), a comparator and six equal sized capacitors of moderate value for fully differential approach. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of an switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the integrating capacitor. ADC being fully differential, has a wide input range and is largely parasitic insensitive. As a stand alone data converter it has a small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8V supply, has ENOB of 9.5 at Nyquist frequency. The area occupied by the designed ADC is 0.05mm2, resulting in an AE as low as 69.32 μm2/code. It is found that the designed ADCs are having better AE as compared to state of the art binary weighted capacitive (BWC) and NBWC SAR ADCs in the literature. These designs are also useful to build high resolution, low power, high speed ADCs such as pipelined, sub-ranging, folding and interpolating ADCs.