A Digital Hearing Aid ASIC With Efficient 18-Band ANSI S1.11 Filter Bank and Dynamic Range Compression Algorithms

Abstract

According to World Health Organization, 466 million people (more than 5 percent of the world population) have disabling hearing loss. A Digital hearing aid consists of analog front end and digital signal processing blocks along with transducers. The incoming sound signal captured by the microphone is given to an analog to digital converter (ADC). The digital output from the ADC is processed by the digital signal processor (DSP) and the processed signal is converted back to analog using a digital to analog converter (DAC) before sending it to the receiver. In this work, the design of a signal processing ASIC, which can perform the task of auditory compensation and the signal compression in a digital hearing aid is presented. Studies on the features of current state of the art techniques suggest a requirement for further optimisation in the area of filter bank and dynamic range compression algorithms. In this work, a new filter bank architecture and new expressions addressing the e ects of gain compression stage on the attack and release time decay coe cients of dynamic range compression algorithm are proposed. In dynamic range compression, by using the proposed equations for estimating the decay coe cients at the algorithm level, the errors that occur at the output with conventional method are totally removed to meet the ANSI S3.22 specifications for hearing aids. At architectural level, eight di erent architectures for the DRC algorithm were compared and conclusions are drawn on the selection of the features of DRC based on the hearing aid requirement. Based on the results, we propose to use an absolute level detector based DRC without smoothing stage for a low power hearing aid application. Interpolated Finite Impulse Response (IFIR) technique was used to develop the proposed 18-band ANSI S1.11 filter bank architecture. Since IFIR technique was used, the hardware implementation of the entire structure became less complex compared to other architectures. The proposed algorithm requires 50% lesser number of filter coe cients compared to other ANSI S1.11 architectures. The proposed algorithm was implemented using standard cell based design flow and the design was tested with NAL-NL2 gain prescription formula for 8 di erent audiograms corresponding to di erent hearing losses. The test results show that the maximum matching error is less than 1 dB. The major contribution of this thesis is the complete hardware implementation of 18-band ANSI S1.11 iii filter bank, as it is not reported in literature to best of our knowledge. The proposed filter bank combined with DRC consumes a total power of 0.39 mW for 65 nm technology. The design was verified in real-time using two FPGAs, one of them modeled as the proposed hearing aid DSP and the other as an external audio CODEC. The hearing aid chip was provided with an SPI protocol for interfacing with the external audio CODEC. The design was also ported to SCL 180 nm technology to fabricate a prototype ASIC.