Design of High Throughput Digital Circuits using Novel Asynchronous Pipeline Methods

Abstract

Pipelining is a key technique that has enhanced the concurrency and throughput of all modern digital systems. Pipelining methods are broadly classi ed as synchronous and asynchronous based on the nature of synchronization present between pipeline stages. In the synchronous design style, a global clock signal provides synchronization among stages, and this design style has been predominating the digital world for several decades. However, the designers are switching their interest from synchronous to asynchronous design due to the problems associated with the clock distribution at lower technology nodes (ex: managing clock skew, wasteful clock power). As there is no global clock in the asynchronous design, it provides freedom from clock-related issues. In addition to this, the asynchronous design also has interesting properties like low power consumption, high performance, reduced electromagnetic emission, modularity, and the capacity to process variable data rate signals. This research work introduces two novel high throughput asynchronous pipeline methods, suitable for gate-level pipelined systems. The proposed methods, named as Early Acknowledged Hybrid (EA-Hybrid) and high capacity hybrid pipeline with post detection (PD-Hybrid), use hybrid data path, that can combine the robustness of dual-rail encoding and simplicity of single-rail encoding schemes. The domino logic style has been adopted for constructing the logic gates in each pipeline stage, as it can provide the latch-less feature. The control path of EA-Hybrid is built based on highspeed early acknowledgment protocol, whereas in PD-Hybrid it is built based on simple and robust 4-phase protocol. Further, both the proposed pipeline styles allow their logic gates into a special state called isolate phase in addition to precharge and evaluation phases. The isolate phase leads to improvement in pipeline throughput as well as storage capacity. Di erent digital circuits like FIFO, Ripple carry adder, array multiplier, and FIR lter are designed based on proposed pipeline styles and simulated using cadence tool suite.