Micro-Architectural support for High Availability of NoC-based MP-SoC

Abstract

In this paper, we focus on increasing the availability of Multi-Processor System on Chip (MP-SoC) for executing user applications, even when some components of the system are faulty. A Network-on-Chip (NoC) provides high bandwidth communication substrate for the multitude of components/modules in such MP-SoCs. Health of such MP-SoC, and hence its availability, is largely dependent on the health of the NoC. We consider an NoC comprising a bidirectional toroidal mesh interconnection of routers. We use a distributed built-in-self-test to identify faulty communication links. We use information so obtained to determine healthy subsystems that can be made available for executing user applications. This feature is key for enhancing availability of MP-SoCs. We realize this feature as a micro-architectural enhancement in MP-SoC that incurs an insignificant hardware overhead of less than 2%. Latency incurred for analyzing availability of MP-SoC is also insignificant. We functionally validate our proposal by emulating the system on a FPGA device and demonstrate increase in availability of the MP-SoC. © 2019 IEEE.