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DC Field | Value | Language |
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dc.contributor.author | Mudadla, D. | |
dc.contributor.author | Sandeep, N. | |
dc.contributor.author | Rao, G.R. | |
dc.date.accessioned | 2020-03-30T10:22:26Z | - |
dc.date.available | 2020-03-30T10:22:26Z | - |
dc.date.issued | 2015 | |
dc.identifier.citation | 4th IEEE Sponsored International Conference on Computation of Power, Energy, Information and Communication, ICCPEIC 2015, 2015, Vol., , pp.123-128 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/8581 | - |
dc.description.abstract | The performance of multilevel inverter is high compared to the classical two level inverters owing to their reduced total harmonic distortion, and lower electromagnetic interference. However the setbacks of multilevel inverter are increased number of power devices, complex PWM and gating circuitry. In this paper, a new multilevel inverter topology, capable of generating large number of levels with fewer number of power switches, gating circuits and power diodes is proposed. In contrast to classical multilevel topologies, the presented topology consequences in reduction of the number of power devices and conduction losses. The proposed topology is asymmetrical, employing isolated dc sources of voltage ratio 421 (Binary fashion). Staircase control PWM at fundamental frequency is employed for the gating of power switches makes it suitable in applications like flexible alternative current transmission systems (FACTS), renewable energy sources, drives control and vehicle propulsion system. The structure of the proposed inverter is modular and thus best suited for PV applications. Detailed simulation is carried out using MATLAB/SIMULINK platform and simulation results are presented. � 2015 IEEE. | en_US |
dc.title | Novel asymmetrical multilevel inverter topology with reduced number of switches for photovoltaic applications | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
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