A 0.5V 300?W 50MS/s 180nm 6bit Flash ADC using inverter based comparators

Abstract

This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 ?W. � 2012 Pillay Engineering College.