YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS

Abstract

In this paper, we present an FPGA based NoC simulation framework, YaNoC, that supports the creation of standard and custom topologies, design of routing algorithms, generation of various synthetic traffic patterns, and exploration of a full set of microarchitectural parameters. The framework supports all standard minimal routing algorithms for conventional NoCs and implements table based routing to support the creation of new routing algorithm. A custom topology called Diagonal Mesh (DMesh) has been evaluated using table based and a modified version of the XY routing algorithm. Mesh and DMesh topologies saturate at the injection rates of 45 % and 55 %. We find that the Table based routing implementation consumes 0.98� fewer hardware resources than the conventional XY routing. We observed the speedup of 2548� compared to the Booksim software simulator. YaNoC achieves speedup of 2.54� and 25� with respect to CONNECT and DART FPGA based NoC simulators. � 2018 IEEE.