Design of Energy Efficient, Variable Resolution, Hybrid Analog to Digital Converters for Low Frequency Applications

Abstract

The advancements in digital technologies made signal processing much easier and provide complex functionalities. The analog to digital converter (ADC) helps to convert the real time data obtained through sensors into digital data. The power consumed by these sensor nodes should be as low as possible in order to improve the battery life. Thus, this research mainly focuses on the design techniques, methodologies, and circuit topologies of ADC with emphasis on minimization of energy consumption and area. Initially, a fully di erential most signi cant bit (MSB) capacitor splitting switching technique for binary weighted capacitive digital to analog con- verter (DAC) in successive approximation register (SAR) ADC is proposed to reduce the energy consumption and area. Also, with this switching technique, one can achieve the same dynamic range as the conventional one, with half of the supply voltage as compared to the existing tech- niques. This makes the proposed switching method suitable for ultra low voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled in MATLAB. The results show that the proposed switching technique reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional one. The circuit level implementation of 10-bit SAR ADC is simulated in UMC 90nm CMOS 1P9M process technology with a supply voltage of 0.5 V . It achieved signal to noise and distortion ratio (SNDR) of 55.93 dB, spuri- ous free dynamic range (SFDR) of 77.17 dB. The Walden gure of merit (FoMW) is calculated as 38.67 fJ/conv. Furthermore, this research presents a switched capacitor based SAR ADC using a passive reference charge sharing and charge accumulation. For N- bit resolution, the fully di erential version of this architecture needs only 6 capacitors, which is a signi cant improvement over conventional binary weighted SAR ADC. The proposed SAR ADC is designed and laid out in UMC 180nm 1P6M CMOS technology with a supply voltage of 1.8 V for a target resolution of 11 bit. The total design occupies an area of 568 m x 298 m and consumes a power as less as 0.28 W. It is found that the integral non-linearity (INL) and di erential non-linearity (DNL) of this v ADC are in the range +0.35/-0.84 least signi cant bit (LSB) and +0.1/- 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC o ers an e ective number of bits (ENoB) of 10.14 and FoMW of 0.12 pJ/conv-step. Finally, a novel switched capacitor integrator based variable resolution hy- brid ADC architecture is proposed. The ADC resolution is programmable from 8-15 bit using a 3- bit control bus (res[2 : 0]). It operates in SAR mode for 8-11 bit resolutions and as the rst-order delta sigma modulator (DSM) with a multi-bit quantizer in 12-15 bit resolutions. A mathematical relationship showing the e ect of mismatch of capacitors on ADC linearity is derived. A fully di erential folded cascode (FC) OTA is designed with programmable unity gain bandwidth (UGB) and slew rate. The proposed ADC, designed and laid out in UMC 180nm standard CMOS technology with a supply voltage of 1.8 V , occupies an area of 0.228mm2. It exhibits SNDR of 45{86 dB and consumes a power of 0.86{98 W across target resolutions (8{15 bits).