Low Voltage, Low Power Integrated Continuous Time Filters for Low Frequency Applications

Abstract

This research presents various designs of low voltage, low power continuous time lters for low frequency applications. Di erent lter topologies such as Transconductor-Capacitor (Gm􀀀C), source follower (SF), voltage follower (VF) and log domain have been explored. UMC 180 nm and UMC 65 nm CMOS technologies are used to design these lters and simulations are carried out in Cadence Virtuoso tool. Initial part of the thesis outlines three di erent proposed designs of bulkdriven transconductors (Transconductor I, II and III) operating with very low supply voltages. Transconductor I operates with a supply voltage of 0.5 V and its transconductance (Gm) can be tuned from 8 nS to 90 nS. A 2nd order Gm 􀀀 C Butterworth low-pass lter (LPF) with cuto frequency tunable from 74 Hz to 820 Hz is used as the test-vehicle for this Transconductor I. Transconductor II operates from a 0.8 V supply voltage. A 2nd order Gm􀀀C Butterworth LPF with a cuto frequency of 100 Hz is designed using this Transconductor II. It o ers a dynamic (DR) of 55.1 dB while consuming a power of 47 nW. A low power proportional to absolute temperature (PTAT) current reference circuit is designed to make cuto frequency of this lter independent of temperature. DR and Figure-of- Merit1 (FoM1) of these 2nd order Gm􀀀C lters are comparable with many other lter designs reported in the literature. Transconductor III operates with an ultra low supply voltage of 0.3 V. A 4th order Gm􀀀C Butterworth LPF is designed using Transconductor III. This lter consumes a power as low as 2.4 nW and o ers a Figure-of-Merit2 (FoM2) of 6.2 10􀀀15. Major area of lter circuits is occupied by capacitors. A simple technique to increase the time constant of a low frequency lter without using large capacitors is proposed. Using the proposed technique, 2nd order SF and log domain LPFs are designed. The SF LPF o ers a DR of 61.85 dB and consumes a power as low as 8 nW. The capacitance value is reduced by a factor of more than 40 times with the use of this time constant enhancement technique in the design of SF and log domain lters. In order to bias the SF LPF, a 5 nA constant current (temperature independent) reference circuit is proposed. v Further, an ultra low voltage bulk-driven VF is proposed. This VF architecture makes it possible to realize a fully di erential circuit without the need of explicit common mode feed back (CMFB) circuit. A 4th order LPF with cuto frequency tunable from 50 Hz to 250 Hz is designed using this bulk-driven VF. The lter achieves the lowest FoM2 among the low frequency nW-class lter designs. The functionality of this VF LPF is demonstrated by testing an ECG signal. The thesis also proposes a couple of designs of PTAT current reference circuits. A 0.8 V current reference circuit with improved supply voltage sensitivity is designed to generate a 5 nA current. In addition, a 1 nA switched capacitor based PTAT current reference circuit is designed with a supply voltage of 0.5 V.