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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hanumantha Rao G. | |
dc.contributor.author | Muhammed Mansoor C.B. | |
dc.contributor.author | Rekha S. | |
dc.date.accessioned | 2021-05-05T10:15:46Z | - |
dc.date.available | 2021-05-05T10:15:46Z | - |
dc.date.issued | 2019 | |
dc.identifier.citation | 2019 Global Conference for Advancement in Technology, GCAT 2019 , Vol. , , p. - | en_US |
dc.identifier.uri | https://doi.org/10.1109/GCAT47503.2019.8978311 | |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/14776 | - |
dc.description.abstract | This paper presents a low voltage, low power Proportional to Absolute Temperature (PTAT) current reference circuit with improved supply voltage sensitivity. The proposed circuit is designed and laid out in UMC 65 nm CMOS technology and simulated using Cadence Virtuoso. It generates a reference current (Iref) of 5 nA at 0.8 V supply voltage (Vdd) at room temperature (27°C). Composite transistors are used to improve the supply voltage sensitivity when compared to a traditional beta-multiplier circuit. The current reference circuit consumes a power of 8 nW and follows PTAT characteristics in the temperature range of 0°C to 80°C. The supply voltage sensitivity of Iref is 2.6 %/V, which shows that the proposed circuit is less sensitive to supply voltage variations. © 2019 IEEE. | en_US |
dc.title | A 0.8 V, 5 nA PTAT current reference circuit with improved supply voltage sensitivity | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | 2. Conference Papers |
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