Design of Low Power Successive Approximation Register Analog-To-Digital Converter

Abstract

Battery operated electronic devices are severely constrained by power dissipation and voltage. Portable devices, in particular, medical implants and wireless sensors insist on smaller die size. Analog-to-digital converter (ADC) interfaces the real analog signal to the digital domain. Being the key component in these integrated circuits, ADC’s design has to meet the said constraints. This thesis addresses the design challenges, strategies and circuit techniques of ultra-low-power and area efficient SAR ADCs. In the said applications, since the conversion speed requirements are in the range of few Hz to MHz, a successive approximation register (SAR) ADC seems to be most appropriate. SAR ADCs are usually implemented using binary weighted capacitors. The ADC at medium-to-high resolution is limited by capacitor mismatch, which eventually is the bottleneck. The size of a capacitor array in itself is an indicator of power and area performance of the SAR ADC. As a first step towards minimizing power dissipation, capacitor matching is improved by having nonbinary weighted capacitors. Second, efforts are made to remove the dependency of power dissipation on capacitor array. Third, parasitics and thermal noise affecting conversion accuracy are suitably addressed. The said strategies are infused in the proposed two novel SAR ADC architectures. To demonstrate the efficacy, a 9 bit 100 kS/s 1 V dual capacitor array SAR ADC and an 8 bit 780 kS/s ±0.35 V switched capacitor based SAR ADC are implemented in CMOS 90 nm technology node. The performances are verified through simulation of layout extracted netlist. Respective figure-of-merit and core area of the implemented dual capacitor array SAR ADC are 14.5 fJ/c-s and 0.00371 mm2. The same, for the case of switched capacitor based SAR ADC are 11.39 fJ/c-s and 0.00145 mm2. Further, the switched capacitor based SAR ADC gels well into ∆Σ modulator loop and its usefulness in noise shaping is verified by simulation of the modelled ADC.