Performance and Reliability Codesign of Drain Extended MOS Devices for Advanced SoC Applications

Abstract

In order to address the demands of advanced functionalities of System on Chips (SoC), interfacing various modules operating at different voltage levels is very much essential. In this work, effectively utilizing the superjunction concept with Drain extended MOS (DeMOS) device is explored for SoC applications. For the first time, design of four different CMOScompatible DeMOS devices, namely, Double and Triple RESURF (Single Superjunction (SJ) devices) and Multiple RESURF (Multiple SuperjunctionsI and II) devices is studied for optimized breakdown voltage and onresistance parameters. The work investigates the primary parameters of the devices relating to p-implant. The device parameters are optimized to maximize the breakdown voltage (VBD) to on-resistance (RON) ratio. The superjunction concept has helped in improving the breakdown voltage by 2× without affecting the on-resistance or has allowed reducing on-resistance by 2.5× without changing the breakdown voltage. Also, hot carrier generation, safe operating area concerns and electrostatic discharge (ESD) reliability behavior is studied for various superjunction DeMOS structures and is compared with conventional DeMOS device. Further, the work is extended to tri-gate structures. Four different Drain extended FinFET devices are proposed, namely, Silicon On Insulator based, p-stop based, well doped with and without p-implant structures. The devices are designed and simulated to explore the suitability of DeFinFETs for submicron high voltage applications. The well doped DeFinFET devices give the best performance metrics compared to SOI and p-stop based DeFinFETs.