Browsing by Author Prabhu, Prasad, B.M.
Showing results 1 to 7 of 7
| Issue Date | Title | Author(s) | Supervisor(s) |
| 2016 | Cache analysis and software optimizations for faster on-chip network simulations | Parane, K.; Prabhu, Prasad, B.M.; Talawar, B. | - |
| 2019 | Design of an adaptive and reliable network on chip router architecture using FPGA | Parane, K.; Prabhu, Prasad, B.M.; Talawar, B. | - |
| 2018 | FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing | Parane, K.; Prabhu, Prasad, B.M.; Talawar, B. | - |
| 2019 | High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks | Prabhu, Prasad, B.M.; Parane, K.; Talawar, B. | - |
| 2020 | LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA | Parane, K.; Prabhu, Prasad, B.M.; Talawar, B. | - |
| 2019 | YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS | Parane, K.; Prabhu, Prasad, B.M.; Talawar, B. | - |
| 2018 | YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS | Parane, K.; Talawar, B.; Prabhu, Prasad, B.M. | - |
